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Number 9

Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7

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  • Bouchaib Marah and WafaΓ’ Bouab Bennani and Pierre Nlend and Adil Sayouti 2016. Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7. International Journal of Applied Information Systems. 10, 8 (April 2016), 49-52. DOI=http://dx.doi.org/10.5120/ijais451392 
  • @article{10.5120/ijais2017451568,
author = {Bouchaib Marah and WafaΓ’ Bouab Bennani and Pierre Nlend and Adil Sayouti},
title = {Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7},
journal = {International Journal of Applied Information Systems},
issue_date = {April 2016},
volume = {10},
number = {},
month = {April},
year = {2016},
issn = {},
pages = {49-52},
numpages = {},
url = {/archives/volume10/number8/892-892-2016451550},
doi = { 10.5120/ijais2016451535},
publisher = {Publisher: Foundation of Computer Science (FCS), NY, USA},
address = {}
}

  • %1 451392
%A Charles B.  Malungu
%A Christopher A.  Moturi
%T Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7
%J International Journal of Applied Information Systems
%@ 
%V 10
%N 
%P 49-52
%D 2016
%I Publisher: Foundation of Computer Science (FCS), NY, USA

Abstract

The MIMO OTA way forward was approved at the 3GPP RAN4 #62bis meeting in Jeju (Korea) [1], and among the remaining works to be accomplished it was highlighted that the channel model had to be validated across methods in order to ensure that a minimal number of artifacts are inserted into the channel model by any given methodology and that the different methods reproduce, and the DUT experiences, the same radio conditions regardless of the methodology.

References

    Keywords

    MIPS, RISC, FPGA, VERILOG HDL.

    Index Terms

    Computer Science
    Information Sciences